Microsoft designs programmable hardware with Project Catapult

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If you ever watch one of Microsoft’s press conferences, or listen to one of their spokespeople sell you on a product, you’ll know that their highest priority has always been to make things work efficiently. Whether it be raising productivity with some of their hardware or creating software that lets you keep things organized, the teams at Microsoft work tirelessly to make sure you can do what you need to get done faster, simpler, and in a more cost effective way.
To bring that productivity to an audience outside of general consumers, namely to developers, Microsoft used the Supercomputing 2015 conference at the University of Texas to announce the availability of Project Catapult clusters. Project Catapult is a groundbreaking Microsoft research venture that “offers a groundbreaking way to vastly improve the performance and energy efficiency of datacenter workloads.” The project hopes to accomplish this with the use of FPGAs, or Field-Programmable Gate Arrays.

An FPGA is, at its core, a chip that defies the limitations that circuits have been stuck with for years. If you’ve ever taken a course in computer science, you know that chips are designed with a specific array of AND gates, OR gates, and NOT gates, which lay out a program that remains in the chip, irreversible. An FGDA, however, bypasses the need to etch these gates directly into the chip, and instead makes it so an engineer can change the nature of the circuit on the fly, without needing to touch hardware.
This provides engineers with an option for building hardware that is not only flexible, not only more energy efficient, but more cost-effective as well. In work published in an ISCA paper in 2014, the Catapult team described how they doubled the throughput of Bing’s search result ranking while raising costs by less than 30%.
Even if you aren’t a developer, or if you are a developer who isn’t interested in utilizing this technology if it becomes widely available, it’s well worth being excited about it. In an interview between Larry Larsen and Doug Berger, it was told to us that these FPGA’s were created to combat the inevitable plateau of Moore’s law, the idea that the number of transistors in a circuit will double every couple of years. If that plateau were allowed to happen, we could be faced with not only a stagnation in the progress of hardware efficiency, but we would also start seeing prices on technology lowering much slower.